87 for(i=0;i<procnbr;i++)
101 step = procnbr / clustnbr;
102 for(i=0;i<clustnbr;i++)
108 for(p=0;p<clustnbr;p++) {
117 for(i=0;i<cblknbr;i++) {
125 for(i=0;i<cblknbr;i++)
131 for(j=symbptr->
cblktab[i].
bloknum;j<symbptr->cblktab[i+1].bloknum;j++)
150 for(i=0;i<simuctrl->
ftgtnbr;i++) {
155 for(i=0;i<simuctrl->
ftgtnbr;i++)
212 for(i=0;i<procnbr;i++)
221 memFree_null(simuctrl->
proctab);
225 for(i=0;i<local_nbthrds;i++)
260 (void)local_nbthrds; (void)procnbr;
262 #ifndef PASTIX_DYNSCHED
263 for(i=0;i<procnbr;i++)
273 for(i=0;i<local_nbthrds;i++)
280 for(i=0;i<clustnbr;i++)
282 for(j=0;j<clustnbr;j++) {
290 memFree_null(simuctrl->
ftgttab);
293 memFree_null(simuctrl->
tasktab);
294 memFree_null(simuctrl->
proctab);
295 memFree_null(simuctrl->
clustab);
296 memFree_null(simuctrl->
ownetab);
297 memFree_null(simuctrl->
cblktab);
298 memFree_null(simuctrl->
bloktab);
299 memFree_null(simuctrl);
BEGIN_C_DECLS typedef int pastix_int_t
Processor candidate group to own a column blok.
pastix_int_t * extendint_Init(ExtendVectorINT *, pastix_int_t)
Initialize the extendVector structure with the initial size given.
void extendint_Exit(ExtendVectorINT *)
Free the extendVector structure.
The extend integer array structure.
void pqueueExit(pastix_queue_t *)
Free the structure associated to the queue.
int pqueueInit(pastix_queue_t *, pastix_int_t)
Initialize the queue structure with an initial space to store the elements.
pastix_int_t infotab[FTGT_MAXINFO]
pastix_queue_t * readytask
pastix_queue_t * futuretask
ExtendVectorINT * tasktab
ExtendVectorINT * ftgtsend
void simuExit(SimuCtrl *, pastix_int_t, pastix_int_t, pastix_int_t)
Free the simulation structure.
pastix_int_t simuRealloc(SimuCtrl *, pastix_int_t, pastix_int_t)
Reallocate the simulation structures to compact them.
static void timerSet(SimuTimer *timer, double t)
Set the timer value.
pastix_int_t simuInit(SimuCtrl *, const symbol_matrix_t *, const Cand *, pastix_int_t, pastix_int_t)
Initialize the simulation structures.
Block structure for the simulation.
Column block structure for the simulation.
Process structure for the simulation.
Fan-in structure for the simulation.
Thread structure for the simulation.
Timer for the simulation.
Control structure for the simulation.